(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of avoiding stress introduced failures in copper metallization.
(2) Description of the Prior Art
Continued reduction in semiconductor device features brings with it continued shrinkage of the widths of interconnect metal in integrated circuits in order to reduce the electrical conductivity of the wiring material. Because of this aluminum, which has been the material of choice since the integrated circuit art began, is becoming less attractive than other, low-resistivity conductors such as copper, gold, and silver. These materials, in addition to their superior electrical conductivity, are also more resistant than aluminum to electromigration, a quality that grows in importance as wire width decreases. These low-resistivity metals however also suffer from a number of disadvantages, such as low diffusion rates and the formation of undesirable inter-metallic alloys and/or recombination centers in other parts of the integrated circuit. Copper has the additional disadvantage of being readily oxidized at relatively low temperatures. Nevertheless, copper is seen as an attractive replacement for aluminum because of its low cost and ease of processing so that the prior and current art has tended to concentrate on finding ways to overcome the limitations that are associated with low-resistivity interconnect materials such as copper.
Materials that are considered for application in the creation of interconnect wire are of aluminum, tungsten, titanium, copper, polysilicon, polycide or alloys of these metals. For comparative purposes the conductivity of copper can be cited as being 6xc3x97107 xcexa9xe2x88x921mxe2x88x921 while typical conductivity of polymers is in the range from between about 10xe2x88x928 to 107 Siemen/meter (S/m). As an example, polyacetylene has an electrical conductivity in excess of 4xc3x97107 xcexa9xe2x88x921mxe2x88x921, which approaches the conductivity of copper of 6xc3x97107 xcexa9xe2x88x921mxe2x88x921.
Copper has a relatively low cost and low resistivity, it also however has a relatively large diffusion coefficient into silicon dioxide and silicon. Copper from an interconnect may diffuse into the silicon dioxide layer causing the dielectric to be conductive, decreasing the dielectric strength of the silicon dioxide layer. Copper interconnects are therefore typically encapsulated by at least one diffusion barrier for the prevention of copper diffusion into surrounding dielectric layers. Silicon nitride is a known diffusion barrier to copper, but the prior art teaches that the interconnects should not lie on a silicon nitride layer because it has a high dielectric constant compared with silicon dioxide. The high dielectric constant causes an undesired increase in capacitance between the interconnect and the substrate.
While copper has become important for the creation of multilevel interconnections, copper lines frequently show damage after chemical mechanical polishing (CMP) and clean. This in turn causes problems with planarization of subsequent layers that are deposited over the copper lines since these layers may now be deposited on a surface of poor planarity. Isolated copper lines or copper lines that are adjacent to open fields are susceptible to damage. While the root causes for these damages are at this time not clearly understood, poor copper gap fill together with subsequent problems of etching and planarization are suspected. Where over-polish is required, the problem of damaged copper lines becomes even more severe.
The above brief summary has highlighted some of the advantages and disadvantages of using copper as in interconnect metal. Continued improvement in semiconductor device performance requires continued reduction of device features and device interconnect lines. This continued reduction in the cross section of interconnect lines results in new stress patterns within the interconnect lines. The invention addresses the application of copper interconnect lines where these interconnect lines are part of overlying layers of interconnect metal that are connected by vias between adjacent layers of copper traces. The vias make contact to overlying or underlying layers of patterned copper interconnections. Where these patterned copper interconnection comprise relatively wide interconnect lines, these wide interconnect line tend to exert a relatively large force on the thereto connected copper vias. This large force, caused by internal stress in the wide interconnect lines, is a cause for poor and unreliable interfaces between the copper vias and the thereto connected wide interconnect lines. The invention addresses this concern and provides a method whereby stress related failures in the interface between copper vias and adjacent and therewith connected wide copper interconnect lines is eliminated.
A principle objective of the invention is to create stress-free interconnect metal of copper.
Another objective of the invention is to eliminate the occurrence of stress in copper interconnect vias by creating slots in interconnect metal traces that are selectively located with respect to the copper interconnect via.
Yet another objective of the invention is to eliminate the occurrence of localized stress migration problems in interconnect metal lines having a width of 2 to 3 microns that are connected to isolated, single vias.
Yet another objective of the invention is to create copper interconnect lines of improved polishing performance.
In accordance with the objectives of the invention a new method is provided for the creation of interconnect metal. Current industry practice is to uniformly add slots to wide and long copper interconnect lines, this to achieve improved CMP results. These slots, typically having a width in excess of 3 xcexcm and having a length in excess of 3 xcexcm, are added to interconnect lines having a width that is equal to or larger than 12 xcexcm. This approach however does not, due to its lack of selectivity of the location of the slots, solve problems of localized stress that are associated with isolated single vias connecting to the metal lines. For this reason, the invention provides for the addition of one or more localized slots adjacent to isolated vias that are connected to bottom or top metal lines that are no wider than about 2 microns.
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